1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor and a method of manufacturing the same.
2. Description of the Related Art
Recent advances require semiconductor devices to process larger amounts of data in shorter amounts of time. As a result, it is necessary to increase integration degree and performance of the semiconductor device. In a general semiconductor device, an electron is stored in a capacitor, so that the capacitor is also required to be scaled down in size and to have increased capacitance.
A conventional capacitor includes a lower electrode, an upper electrode and a dielectric layer interposed between the lower and upper electrodes. The lower electrode generally comprises polysilicon, and the dielectric layer usually comprises a tantalum compound or a compound including barium (Ba) and strontium (Sr). In general, the upper electrode comprises titanium (Ti), tungsten (W), platinum (Pt) or polysilicon.
Capacitance C of a capacitor is expressed as the following equation (1):C=εAs/d  (1)
In the above equation (1), C denotes capacitance of the capacitor, ε denotes dielectric constant of a dielectric material in the capacitor, As denotes surface area of an electrode of the capacitor and d denotes thickness of the dielectric material in the capacitor.
According to equation (1), the capacitance of a capacitor may be increased (a) by reducing the thickness d of the dielectric material in the capacitor, (b) by increasing the surface area As of the electrode of the capacitor, or (c) by using a dielectric material having a high dielectric constant ε.
Among the three methods for increasing the capacitance of the capacitor, increasing the surface area As of the electrode has been most intensively researched until now.
According to a conventional planar type capacitor, an effective surface area of the capacitor is substantially identical to a projection area of the upper or the lower electrode; thus, increasing the capacitance of the capacitor necessarily requires an increase of the projection area of the electrode. As a result, there is a problem in the conventional planar type capacitor that scale down of the size of the capacitor cannot be practically achieved. A stepped cylindrical capacitor has been developed for solving the basic problem of the planar type capacitor as disclosed in U.S. Pat. No. 6,320,244 (issued to Glenn B. Alers, et al.) and U.S. Pat. No. 6,346,454 (issued to Chun-Yung Sung, et al.).
FIG. 1 is a view illustrating a conventional stepped cylindrical capacitor of a semiconductor device with reference to the above U.S. Pat. No. 6,320,244.
Referring to FIG. 1, a semiconductor device such as an integrated circuit (IC) includes a stepped cylindrical capacitor 24 formed on a substrate 30 including a silicon layer (not shown) on a surface thereof. First, second and third insulation layers 32, 40 and 42, respectively, are sequentially formed on the silicon layer of the substrate 30. A lower wiring 34 is formed in the first insulation layer 32 with a predetermined width. Etching stop layers (not shown) are formed between the first and the second insulation layers 32 and 40, and between the second and the third insulation layers 40 and 42, respectively.
A first opening is formed to have a first width in the third insulation layer 42 and a second opening is formed to have a second width smaller than the first width in the second insulation layer 40. The second opening is continuously connected to the first opening. Then, a lower electrode 44, a dielectric layer 45 and an upper electrode 46 are sequentially formed along sidewalls and bottoms of the first and second openings. A conductive material is deposited on a surface of the third insulation layer 42 to a sufficient thickness to fill up the first and second opening, so that a conductive layer is formed on the third insulation layer and the first and second opening are filled with the conductive layer. Then, the conductive layer is removed and planarized by a chemical mechanical polishing (CMP) process until the top surface of the third insulation layer 42 is exposed; thus, the conductive layer remains only in the first and second openings on the upper electrode to thereby accomplish the stepped cylindrical capacitor 24. The lower electrode and the upper electrode are separated from each other by the CMP process, and are exposed on the same plane.
When operating the stepped cylindrical capacitor 24, a voltage is applied to both the upper and the lower electrodes 44 and 46 positioned on the same plane. However, a current leaks from an end portion of the upper and lower electrodes since both of the electrodes are positioned on the same plane when the voltage is applied. The leakage current causes damage to the capacitor 24, and leads to a fatal failure such as a malfunction of the IC or a breakdown of the IC.
Accordingly, there is still needed an improved stepped cylindrical capacitor for preventing the leakage current from the end portion of the electrodes.